PIN diode switches, when used in high frequency switching applications, can be configured is many different ways. The most common configuration is a series-shunt switch to achieve a multiple throw, broadband, fast switching and good isolation with moderate insertion loss and moderate power handling capabilities. However, as the upper RF frequency increases above 8 or 10 GHz performance is limited by several factors, including the minimum achievable PIN diode parameters, mainly the junction capacitances. To lessen the effect of the junction capacitance it is standard practice in the prior art to mount the shunt PIN diode as close as possible to each series PIN diode. But no matter how close the shunt and series PIN diodes are to each other, there is still a length of transmission line required to make the connection. As the RF or data signal frequency is increased, this length of transmission line degrades the performance and ultimately creates an upper frequency limit. This limit is classically around 18 or 20 GHz.
It is a principal object of the present invention to minimize losses in efficiency as the frequency of the data signal is increased in order to raise the upper frequency limit.
It is also an object of the present invention to minimize such losses by relatively simple and inexpensive changes in the layout of the PIN diode switch.